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The instruction set offers extensive support for 1-bit variables, allowing direct bit manipulation in control and logic systems that require Boolean processing. As typical of 8-bit processors, instructions have 8-bit opcodes. Of these, are implemented and 1 is undefined. As well as the opcode, some instructions have one or two additional bytes for data or addresses.

In all, there are 1-byte instructions, 92 2-byte instructions, and 24 3-byte instructions. The Opcode Map in Appendix B shows, for each opcode, the mnemonic, the number of bytes in the instruction, and the number of machine cycles to execute the instruction. They allow specifying the source or destination of data in different ways, depending on the programming situation.

In this section, we'll examine all the addressing modes and give examples of each. Instructions using register addressing are encoded using the three least-significant bits of the instruction opcode to specify a register within this logical address space. Thus, a function code and operand address can be combined to form a short 1-byte instruction.

See Figure a. The assembly language indicates register addressing with the symbol Rn where n is from 0 to 7. For example, to add the contents of Register 7 to the accumulator, the following instruction is used ADD A,R7 and the opcode is B. The upper five bits, , indicate the instruction, and the lower three bits, , the register. Convince yourself that this is the correct opcode by looking up this instruction in Appendix C. What does this instruction do? This instruction moves the 8-bit content of register 7 in the active register bank to the accumulator.

Discussion Appendix C lists all instructions, sorted alphabetically by mnemonic. The binary opcode appears as rrr. The low-order three bits identify the source register, which is R7 in this example. There are four "banks" of working registers, but only one is active at a time. A hardware reset enables bank 0, but a different bank is selected by modifying PSW bits 4 and 3 accordingly.

Some instructions are specific to a certain register, such as the accumulator, data pointer, etc. The opcode itself indicates the register. Consult Appendix C to determine the opcode for this instruction. The bit product is left in the accumulator low byte and register B high byte. An additional byte is appended to the opcode specifying the location to be used. See Figure b. Depending on the high-order bit of the direct address, one of two on-chip memory spaces is selected.

For example, Ports 0 and 1 are assigned direct addresses 80H and 90H, respectively. It is usually not necessary to know the addresses of these registers; the assembler allows for and understands the mnemonic abbreviations "P0" for Port 0, "TMOD" for timer mode register, etc. Some assemblers, such as Intel's ASM51, automatically include the definition of predefined symbols.

Other assemblers may use a separate source file containing the definitions. The direct address of Port 1 90H is determined by the assembler and inserted as byte 2 of the instruction.

The source of the data, the accumulator, is specified implicitly in the opcode. The first byte is the opcode, 75H. The third byte is the immediate data, 55H. This situation arises when manipulating sequential memory locations, indexed entries within tables in RAM, multiple-precision numbers, or character strings. Register or direct addressing cannot be used, since they require operand addresses to be known at assemble-time. The solution is indirect addressing. R0 and R1 may operate as "pointer" registers—their contents indicating an address in internal RAM where data are written or read.

The least-significant bit of the instruction opcode determines which register R0 or R1 is used as the pointer. See Figure c. In assembly language, indirect addressing is represented by a commercial "at" sign preceding R0 or R1. The data are moved from the location whose address is in R0. Since "R0" is specified as the indirect register, "0" is substituted for "i" in the opcode. Indirect addressing is essential when stepping through sequential memory locations.

The test uses 80H, rather than 7FH, because the increment occurs after the indirect move. This ensures the final location 7FH is written to before terminating. An additional instruction byte contains the value.

See Figure d. In assembly language, immediate operands are preceded by a number sign. The operand may be a numeric constant, a symbolic variable, or an arithmetic expression using constants, symbols, and operators. The assembler computes the value and substitutes the immediate data into the instruction. It is assumed the constant "12" is in decimal notation, since it is not followed by "H.

When initializing the data pointer, a bit constant is required. Hexadecimal: 24H, 0FH. The second byte of the instruction is the immediate data.

A relative address or offset is an 8-bit signed value, which is added to the program counter to form the address of the next instruction executed. The relative offset is appended to the instruction as an additional byte. See Figure 3-le. Prior to the addition, the program counter is incremented to the address following the jump instruction; thus, the new address is relative to the next instruction, not the address of the jump instruction.

Normally, this detail is of no concern to the programmer, since jump destinations are usually specified as labels and the assembler determines the relative offset accordingly. What are the machine language bytes for this instruction? The second byte is an 8-bit signed value which is the relative offset.

Since we are jumping "ahead" in memory for this example, the offset is positive. As shown in Figure , the source address is the address "after" the jump instruction. The offset is added to this value to obtain the destination address for the jump.

To what address will the jump occur? The source address for the jump is the address following the jump instruction, which for this example is H. Since our offset is negative and our address is 16 bits, we must "sign-extend" the offset and express it as a bit number: 0FFF6H. This is discarded. These 2-byte instructions allow branching within the current 2K page of code memory by providing the 11 least-significant bits of the destination address in the opcode AA8 and byte 2 of the instruction A7-A0.

See Figure f. The upper five bits of the destination address are the current upper five bits in the program counter, so the instruction following the branch instruction and the destination for the branch instruction must be within the same 2K page, since AA11 do not change.

The upper five bits in the program counter will not change when this instruction executes. Absolute addressing offers the advantage of short 2-byte instructions, but has the disadvantages of limiting the range for the destination and providing position-dependent code. The subroutine to which the call is directed begins in memory location 17A6H.

Solution F1H, A6H Discussion As found in Appendix C, the encoding for the ACALL instruction is aaall aaaaaaaa The low-order 11 bits of the destination address are inserted into the instruction with bits placed in the high-order bits of the opcode and with bits forming the second byte of the instruction. The destination address 17A6H is shown below in binary with the low-order 11 bits identified as a group of three bits and a group of eight bits 7-F.

It is this property that identifies the source and destination addresses as falling within the same 2K page. These 3-byte instructions include a full bit destination address as bytes 2 and 3 of the instruction. See Figure g. Position-dependence is a disadvantage because the program cannot execute at different addresses. If, for example, a program begins at H and an instruction such as LJMP H appears, then the program cannot be moved to, say, H. The LJMP instruction would still jump to H, which is not the correct location after the program has been moved.

The high byte of the destination address 8AH is in byte 2, and the low byte 0F2H is in byte 3. See Figure h. Jump tables or look-up tables are easily created using indexed addressing. The instruction is only one byte long, with the opcode specifying both the operation and the addressing mode. This instruction moves a byte of data from code memory to the accumulator. The address in code memory is found by adding the index the present state of the accumulator to the base register the data pointer.

When the instruction finishes executing, the index is lost because it is overwritten with the value moved from code memory. Once you are familiar with the instruction set, this chart should prove a handy and quick source of reference. We continue by examining instructions in each functional grouping from Appendix A.

Discussion On the surface, this example seems straightforward: Given two values, add them and obtain the sum. However, there are some interesting conceptual issues that are important to understand. Let us begin by expressing the initial values of the ACC and R3 in decimal.

However, there is a problem. Only you—the programmer— knows for sure. The mechanism to manage different formats of data is provided through the status bits in the PSW. To illustrate this, the addition is worked out below in binary. Note above that carries occurred out of bits 0, 1, 5, and 6.

Carries did not occur out of bits 2, 3, 4, and 7. Because there was no carry out of bit 7, the C carry bit in the PSW is not set after the addition. As for the OV overflow bit, the following description appears in Appendix C for the ADD instruction: "the OV bit is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not out of bit 6; otherwise OV is cleared.

Since a carry did not occur out of bit 3, the AC bit is cleared. Finally, the P bit in the PSW is set or cleared to establish even parity with the accumulator. Because the result in the ACC has three bits equal to one, the P bit is set, bringing the total to four - an even number. Only the OV and P bits are set; the other bits are cleared see Table The second question in this example is, "What is the content of the accumulator in decimal after execution of this instruction?

Because the original problem did not indicate a format or representation for the original data, we cannot answer the question with certainty, hence the "? There are, however, at least two possible answers. The important point is that the meaning or representation scheme in effect is not a characteristic of the CPU, but, rather, it is determined by the way the data are managed by the software.

So, the first instruction above moves one of the bytes to the accumulator to prepare for the operation. The second instruction clears the carry flag in the program status word.

This is required because the only form of the subtract instruction is SUBB—subtract with borrow. For subtract operations, the carry bit serves as a "borrow" bit. The third instruction performs the subtraction, leaving the result in the accumulator. The fourth instruction moves the result into R7. The provides powerful addressing of its internal memory space.

Any location can be incremented or decremented using direct addressing without going through the accumulator. How could this operation be achieved? The second instruction increments the value read which is now in the accumulator , and the third instruction writes the result back to internal RAM. Not only is this instruction sequence longer and slower than the single-instruction equivalent INC direct , the previous value of the accumulator is lost.

One of the INC instructions operates on the bit data pointer. Since the data pointer generates bit addresses for external memory, incrementing it in one operation is a useful feature.

The MUL AB instruction multiplies the accumulator by the data in the B register and puts the bit product into the concatenated B high-byte and accumulator low-byte registers. The A accumulator is left with the value 4 and the B accumulator is left with the value 1. What are the contents of these registers after execution of the following instruction? The P bit in the PSW is set to establish even parity with the accumulator. Since the result is greater than , the overflow flag is set, leaving the PSW containing 05H.

What is the largest value that could be in register B such that the OV bit would not be set after executing the following instruction? The overflow flag is set following MUL if the product is greater than The first is in internal memory locations 40H and 41H, and the second is in locations 42H and 43H. The mostsignificant digits are in locations 40H and 42H. Even though the 's arithmetic instructions operate on bytes, it is possible to add or subtract larger data, for example, 16 bits or 32 bits.

This is also true for binary-coded decimal numbers. To add two 4-digit numbers, two byte additions are required. The trick in multiprecision arithmetic is in propagating carries from byte to byte. During addition, carries are naturally propagated from bit to bit within a byte, but from byte to byte, a carry—if it occurs—is temporarily held in the C bit in the PSW.

Since a carry cannot occur into the low-order bytes, the first add instruction above is the generic "ADD. Both add instructions are followed by DA A to perform the necessary adjustment for binary-coded decimal values. This is illustrated below. The others take two machine cycles. Logical operations can be performed on any byte in the internal data memory space without going through the accumulator.

The eight bits at Port 1 are read; then each bit read is exclusive ORed with the corresponding bit in the immediate data. Since the eight bits of immediate data are all 1s, the effect is to complement each bit read e.

The result is written back to Port 1. The carry flag rotates into ACC. This is a useful operation in BCD manipulations. The SWAP A instruction swaps the low-order and high-order nibbles in the accumulator, and, as noted in Appendix C, this is equivalent to a 4-bit rotate operation. To undo the fourth rotation, a final rotate to the right is used. Although the effect of solutions a and b is the same, they are slightly different in terms of memory usage and execution speed.

All instructions above are 1-byte, 1-cycle instructions see Appendix C , so solution a uses three bytes of memory and takes three CPU cycles to execute. Solution b uses only two bytes of memory and executes in two CPU cycles. The difference may seem minuscule, but in the world of embedded control systems, squeezing every last ounce out of a program is often a design requirement.

Bit 7 and bit 0 are 3. The approach taken in the solution is to build the new value in the B register by successively shifting a bit out of the accumulator into the carry bit and then shifting the same bit back into the B register. To reverse the bit pattern, the first shift is "to the left" and the second shift is "to the right. A final XCH positions the correct result in the accumulator. Note: The B register is at direct address 0F0H.

A feature of the MCSTM architecture differing from most microprocessors is that the stack resides in on-chip RAM and grows upward in memory, toward higher memory addresses. PUSH and POP use direct addressing to identify the byte being saved or restored, but the stack itself is accessed by indirect addressing using the SP register. What internal RAM locations are altered, and what are their new values after executing the following instructions?

The stack pointer is incremented twice as a result of the two instructions, so its final value is 09H. Data transfer instructions include a bit MOV to initialize the data pointer DPTR for look-up tables in program memory, or for bit external data memory accesses.

DPL is at address 82H. The disadvantage in using bit addresses is that all eight bits of Port 2 are used as the high-byte of the address bus. On the other hand, 8-bit addresses allow access to a few Kbytes of RAM, without sacrificing all of Port 2.

See Chapter 2, "Accessing External Memory. The second instruction reads a byte from external memory location 10F4H and places it in the accumulator. The third instruction transfers the byte read to register 6. Note that the MOVX instruction must use the accumulator as either the source or destination of data. The fourth instruction increments the data pointer, leaving it pointing to the second of the two external addresses to be read.

The fifth instruction reads a byte from external memory location 10F4H and places it in the accumulator. The sixth instruction transfers the byte read to register 7. Since they access program memory, the look-up tables can only be read, not updated. The mnemonic is MOVC for "move constant.

The number of the desired entry is loaded into the accumulator and the data pointer is initialized to the beginning of the table. The table is usually accessed through a subroutine. First, the number of the desired entry is loaded into the accumulator, and then the subroutine is called. The table immediately follows the RET instruction in program memory. Incrementing the accumulator will effectively bypass the RET instruction when the table look-up takes place.

Note however that even though we would expect to get a table of entries when using this technique, we only get entries in this case since we lose one entry due to the effect of the INC A instruction. Consider the entry number of that is moved into the accumulator. Therefore, valid entries are only from 0 to Enter the subroutine with the integer in A,and return with the square of the integer in A.

Write two versions of the subroutine: a using a look-up table, and b without using a lookup table. Then c illustrate a call sequence to convert 6 to its square, Solution a. For this example, however, there is an interesting alternative approach, as shown in b. Since the B accumulator is overwritten by the second instruction, it is first saved on the stack and then restored from the stack before returning from the subroutine. In comparing solutions a and b , we find an interesting tradeoff.

Solution a is 13 bytes, including the look-up table, whereas solution b is only eight bytes. However, solution a executes in five CPU cycles, whereas solution b executes in 11 cycles.

The tradeoff is that solution a is faster which is good! This tradeoff would be more pronounced if the look-up table was large, because every entry adds one byte to the size of the routine. In many situations, the relationship between the index to a table and the entries within a table is not as simple as in this example, and using a look-up table is the only viable implementation. All port lines are bit-addressable, and each can be treated as a separate single-bit port.

The instructions that access these bits are not only conditional branches but also a complete repertoire of move, set, clear, complement, OR, and AND instructions. Such bit operations—one of the most powerful features of the MCSTM family of microcontrollersare not easily obtained in other architectures with byte-oriented operations.

The available Boolean instructions are shown in Appendix A. Bits may be set or cleared in a single instruction. The carry bit in the program status word PSW is used as the single-bit accumulator of the Boolean processor. Bit instructions that refer to the carry bit as "C" assemble as carry-specific instructions e.

The carry bit also has a direct address, since it resides in the PSW register, which is bit-addressable. Like other bitaddressable SFRs, the PSW bits have predefined mnemonics that the assembler will accept in lieu of the bit address.

The carry flag mnemonic is "CY," which is defined as bit address 0D7H. In the latter case, the second byte is the direct address of the specified bit—the carry flag.

Suppose one wanted to compute the logical AND of the input signals on bit 0 and bit 1 of Port 1 and output the result to bit 2 of Port 1. This logical relationship is illustrated in Figure If the logic operation in Figure is implemented using a typical electronic logic circuit, such as a 74AL, then the input-to-output propagation delay is on the order of 7 ns. This is the time from an input signal transition to the correct logic level appearing at the output.

What is the worst-case propagation delay for the circuit in Figure if implemented using the software above? Figure will assist in answering this question. The worst-case scenario is that P1. The change is not sensed until the next pass through the loop. The correct output state appears at "B" in the figure. The solid line in Figure illustrates the sequence of instructions for the worst-case scenario.

Obviously there is "no contest" in comparing the speed of a microcontroller with speed of electronic logic circuits.

The instructions are shown below. Complementing C completes the operation. JBC jump if bit set then clear bit executes the jump if the addressed bit is set, and also clears the bit; thus, a flag can be tested and cleared in a single instruction.

All PSW bits are directly addressable, so the parity bit or the general purpose flags, for example, are also available for bit-test instructions. These possibilities are enhanced further by the three addressing modes for the program branching instructions. Intel's assembler ASM51 allows the use of the generic JMP mnemonic if the programmer does not care which variation is encoded.

Assemblers from other companies may not offer this feature. Otherwise, it assembles to LJMP. The geneneric CALL instruction see below works the same way. The SJMP instruction specifies the destination address as a relative offset, as shown in the earlier discussion on addressing modes.

The LJMP instruction specifies the destination address as a bit constant. Since the instruction is three bytes long an opcode plus two address bytes , the destination address can be anywhere in the 64K program memory space.

The AJMP instruction specifies the destination address as an bit constant. As with SJMP, this instruction is two bytes long, but the encoding is different. The opeode contains three of the 11 address bits, and byte 2 holds the low-order eight bits of the destination address. When the instruction is executed, these 11 bits replace the low-order 11 bits in the PC, and the high-order five bits in the PC stay the same.

In all cases the programmer specifies the destination address to the assembler in the usual way - as a label or as a bit constant. The assembler will put the destination address into the correct format for the given instruction. If the format required by the instruction will not support the distance to the specified destination address, a "destination out of range" message is given. The destination address is computed at execution time as the sum of the bit DPTR register and the accumulator.

Typically the DPTR is loaded with the address of a jump table, and the accumulator acts as an index. Content 0l B8 0l 43 41 76 El F0 What is the beginning and ending address of the 2K block of code memory within which these instructions reside?

Since this instruction uses absolute addressing, the jump destinations must be within the same 2K page as the ACALL instructions. A 2K page is a block of code memory with the upper five address bits the same. The upper five bits in H are B. The upper three bits of the opcode are B and the second byte of the instruction is B. Either instruction pushes the content of the program counter on the stack and loads the program counter with the address specified in the instruction.

Note that the PC will contain the address of the instruction following the CALL instruction when it gets pushed on the stack. The PC is pushed on the stack low-byte first, high-byte second. The bytes are popped from the stack in the reverse order. Assume the stack pointer contains 3AH just before this instruction executes. This is the address to which the program must return at the end of the subroutine, and it is the address that is saved on the stack before branching to the subroutine.

Note that the stack pointer is a special function register located at internal RAM address 81H. There is nothing magical about the way the RET instruction gets back to the main program. It simply "pops" the last two bytes off the stack and places them in the program counter. It is a cardinal rule of programming with subroutines that they should always be entered with a CALL instruction, and they should always be exited with a RET instruction.

Jumping in or out of a subroutine any other way usually fouls up the stack and causes the program to crash. What is the value of the stack pointer after execution of this instruction? Solution 1CH Discussion The return address for the subroutine is 16 bits or two bytes.

The purpose of the RET instruction is to retrieve two bytes from the stack and place them in the program counter, thus allowing the program to continue executing at the location following the call instruction that leads to the subroutine. Regardless of what address this may be, the stack pointer contains two less than its value before RET executed. This means that the two bit values are stored in C and P, respectively, prior to the calling of the subroutine, and the XORed result should be put back in C.

Note, however, that the user specifies the destination address the same way as with the other jumps, as a label or bit constant. The assembler does the rest. There is no 0-bit in the PSW. The DJNZ instruction decrement and jump if not zero is for loop control. Two bytes are specified in the operand field of the instruction, and the jump is executed only if the two bytes are not equal. Another application of this instruction is in "greater than" or "less than" comparisons. The two bytes in the operand field are taken as unsigned integers.

If the first is less than the second, the carry flag is set. If the first is greater than or equal to the second, the carry flag is cleared.

The sole purpose of the compare is to set or clear the carry flag. The JNC instruction decides whether or not the jump takes place. This example is one instance in which the approach to a common programming situation is more awkward than with most microprocessors; however, as we shall see in Chapter 7, the use of macros allows powerful instruction sequences, such as the example above, to be constructed and executed using a single mnemonic.

The reader is encouraged to refer to Appendix C for more examples of using this instruction set. The next three chapters will discuss more programming examples in terms of interacting with the 's on-chip peripherals: the timers, the serial port, and the interrupts. MOV A, -2 c. SETB P2. XLR A, 'S' f. CLR C 3. How many bytes long is this instruction? Explain the purpose of each byte of this instruction.

How many machine cycles are required to execute this instruction? If an is operating from a 16 MHz crystal, how long does this instruction take to execute? If an is operating from a 10 MHz crystal, how long does this instruction take to execute? What is the content of the accumulator after the following instruction executes? RRC A 3. Assume P1. Assume 12 MHz operation. For each program, what is the worst-case propagation delay from an input transition to an out-put transition?

For each program, what is the worst-case propagation delay from an input transition to an output transition? What are the hexadecimal machine language bytes for this instruction? What instruction s would be used? What is the result in accumulator A after the following instruction executes? What does this subroutine do? In how many machine cycles does each instruction execute? How many bytes long is each instruction? Convert the subroutine to machine language.

Note that setting an port pin to"1" turns the corresponding segment "ON. What are the advantages of using look-up tables? Describe how each one works in detail. Assume each instruction is independent of the other. CPL 7FH b. Store the result in internal RAM location 70H. Write comments for each line of code. For example, 5! Write an assembly language program to calculate the factorial of a number that is stored in RAM location 44H.

Put the result of the calculation into RAM location 77H. Write a program to use a look-up table to find the result of 20 log10 x. Round your precomputations to integers. The result rounded off to the nearest integer should be returned in R1 high byte and R0 low byte. Instead, use other instructions to do so. The higher-order byte of the result should be put in R3 while the lower-order byte of the result should be put in R2.

Explain the advantages of using subroutines in your assembly language programs. Write a subroutine called POW that calculates the result of the number in theaccumulator A raised to the power of a number stored in the B register. Return the bit answer in the accumulator, A for the low byte and B register for the high byte. Your subroutine should call the POW subroutine to do the exponentiations raising a number to the power of another number.

Instead, you should call the SUM subroutine to do the additions. Return the total sum in R5. The result should be stored in C. Write the comments for each line of code. Explain what you think the subroutine is used for. The quotient should be stored in A and the remainder in B. This means that the two bit values are stored in C and P prior to the calling of the subroutine, and the X0Red result should be put back in C. Rewrite the subroutine to XOR two bits based on the following methods: a.

Change each bit into a byte and then do XOR on the bytes b. Write the assembly language instructions to reverse the order in which the numbers are stored: 0 is put in 39H, 1 in 38H, etc. We begin with a simplified view of timers as they are commonly used with microprocessors or microcontrollers. A timer is a series of divide-by-2 flip-flops that receive an input signal as a clocking source.

The clock is applied to the first flip-flop, which divides the clock frequency by 2. The output of the first flip-flop clocks the second flip-flop, which also divides by 2, and so on. Since each successive stage divides by 2, a timer with n stages divides the input clock frequency by 2n. The output of the last stage clocks a timer overflow flip-flop, or flag, which is tested by software or generates an interrupt.

The binary value in the timer flipflops can be thought of as a "count" of the number of clock pulses or "events" since the timer was started. The operation of a simple timer is illustrated in Figure for a 3-bit timer. Each stage is shown as a type-D negative-edge-triggered flip-flop operating in divide-by-2 mode i. The flag flip-flop is simply a type-D latch, set by the last stage in the timer.

The count is shown in decimal and is easily verified by examining the state of the three flip-flops. Timers are used in virtually all control-oriented applications, and the timers are no exception. There are two bit timers each with four modes of operation. A third bit timer with three modes of operation is added on the In interval timing applications, a timer is programmed to overflow at a regular interval and set the timer overflow flag.

The flag is used to synchronize the program to perform an action such as checking the state of inputs or sending data to outputs. Other applications can use the regular clocking of the timer to measure the elapsed time between two conditions e.

Event counting is used to determine the number of occurrences of an event, rather than to measure the elapsed time between events. An "event" is any external stimulus that provides a 1-to-0 transition to a pin on the IC.

The timers can also provide the baud rate clock for the 's internal serial port. The timers are accessed using six special function registers. See Table An additional five SFRs provide access to the third timer in the See Table and Table TMOD is not bit-addressable, nor does it need to be.

Generally, it is loaded once by software at the beginning of a program to initialize the timer mode. Thereafter, the timer can be stopped, started, and so on by accessing the other timer SFRs. These bits are used extensively in the examples in this chapter. They are used to detect and initiate external interrupts. Discussion of these bits is deferred until Chapter 6, when interrupts are discussed. Since there are two timers on the , the notation "x" is used to imply either Timer 0 or Timer 1; thus, "THx" means either TH1 or TH0, depending on the timer.

It is not generally used in new designs. The timer high-byte THx is cascaded with the five least-significant bits of the timer low-byte TLx to form a bit timer. The upper three bits of TLx are not used. As clock pulses are received, the timer counts up: H, H, H, etc. The timer continues to count. The LSB toggles at the input clock frequency divided by 2, while the MSB toggles at the input clock frequency divided by 65, i.

The timer low-byte TLx operates as an 8-bit timer while the timer high-byte THx holds a reload value. This mode is convenient, since timer overflows occur at specific periodic intervals once TMOD and THx are initialized.

Timer 0 in mode 3 is split into two 8-bit timers. Timer 1 is stopped in mode 3 but can be started by switching it into one of the other modes. The only limitation is that the usual Timer 1 overflow flag, TF1, is not affected by Timer 1 overflows, since it is connected to TH0. Mode 3 essentially provides an extra 8-bit timer: The appears to have a third timer. When Timer 0 is in mode 3, Timer 1 can be turned on and off by switching it out of and into its own mode 3. It can still be used by the serial port as a baud rate generator, or it can be used in any way not requiring interrupts since it is no longer connected to TF1.

One clocking source is used for interval timing, the other for event counting. A divide-by stage is added to reduce the clocking frequency to a value reasonable for most applications. In most applications, this external source supplies the timer with a pulse upon the occurrence of an "event"—the timer is event counting.

The external clock source comes by way of the alternate functions of the Port 3 pins. Port 3 bit 4 P3. In counter applications, the timer registers are incremented in response to a 1-to-0 transition at the external input, Tx.

The external input is sampled during S5P2 of every machine cycle; thus, when the input shows a high in one cycle and a low in the next, the count is incremented. The new value appears in the timer registers during S3P1 of the cycle following the one in which the transition is detected.

The two possibilities for clocking the timers are shown in Figure We now demonstrate how to start, stop, and control the timers.

TRx is clear after a system reset; thus, the timers are disabled stopped by default. TRx is set by software to start the timers. This is useful for pulse width measurements as follows. Assume INT0 is low but pulses high for a period of time to be measured. INT0 can be programmed to generate an interrupt when it returns low. To complete the picture, Figure illustrates Timer 1 operating in mode 1 as a 16bit timer.

Study the figure and identify the 's timer registers and control bits shown. Tabulate the bit and byte addresses for each.

For the control bits, identify the special function registers that hold them. These bits are usually set and cleared on-the-fly to start and stop the timer or to check its status as appropriate. Thereafter, within the body of a program, the timers are started, stopped, flag bits tested and cleared, timer registers read or updated, and so on, as required in the application.

TMOD is the first register initialized, since it sets the mode of operation. Of course, the timer does not actually begin timing until its run control bit, TR1, is set. The correct value is or 0FF9CH. Since two timer registers must be read, a "phase error" may occur if the low-byte overflows into the high-byte between the two read operations. A value may be read that never existed. The solution is to read the high-byte first, then the low-byte, and then read the high-byte again.

If the highbyte has changed, repeat the read operations. This issue is examined assuming the is operating from a 12 MHz crystal. The on-chip oscillator is divided by 12 and clocks the timers at a rate of 1 MHz. The shortest possible interval is limited, not by the timer clock frequency, but by software. Presumably, something must occur at regular intervals, and it is the duration of instructions that limit this for very short intervals. The shortest instruction on the is one machine cycle or one microsecond.

Table summarizes the techniques for creating intervals of various lengths. Operation from a 12 MHz crystal is assumed. What are the frequency and duty cycle of the waveform? Solution Discussion This program creates a pulse waveform on P1. It might appear at first that the instructions in Figure are misplaced, but they are not.

The period of the waveform can be lengthened by inserting NOP instructions into the loop. Beyond a point, software tuning is cumbersome, and a timer is the best choice to create time delays.

The frequency is Moderate-length intervals are easily obtained using 8-bit auto-reload mode, mode 2. Solution Discussion The program above creates a square wave on P1. The reload value is specified using decimal notation as line 8 , rather than using hexadecimal notation.

The assembler performs the necessary conversion. Note that the timer overflow flag TF0 is explicitly cleared in software after each overflow line Full bit timer mode, mode 1, is required.

The main difference in the software is that the timer registers, TL0 and TH0, are reinitialized after each overflow lines 8 and 9. There is a slight discrepancy in the output frequency in the program above.

This results from the extra instructions inserted after the timer overflow to reinitialize the timer. Such errors do not occur in auto-reload mode, since the timer is never stoppe - it overflows at a consistent rate set by the reload value in TH0. Since there are two timers in the , a program could make use of them to simultaneously generate two different waveforms on separate port pins. The value written into TMOD initializes both timers at the same time.

Even though the timers are running simultaneously, the testing for overflow has to be done in sequence. Timer 0 is checked first since its period is smaller in order to avoid missing its overflows. Notice that Timer 0 is set to operate in mode 2 auto-reload mode so there is no need to reload the count after every overflow. Meanwhile, Timer 1 operates in mode 1 so its count must be reloaded every time an overflow occurs.

Intervals longer than 0. A more practical approach uses one of the timers in bit mode with a software loop counting overflows. The desired operation is performed every n overflows. Write a program that reads the logic level provided by the switch and sounds the buzzer for 1 second for each 1-to-0 transition detected. An inverter is used as a driver since the AI draws 7 mA of current.

The AI costs a few dollars. The main loop in the software consists of six instructions lines In line 10, a one-instruction loop is executed to wait for the input signal on P1. Then another one-instruction loop line 11 executes to wait for the input signal to go low. When this happens, the buzzer sounds for 1 second.

This is implemented in the next three instructions. First, P1. Then the main loop is executed again line The delay subroutine lines uses the technique identified in Table as "16bit timer plus software loops. This delay lines is enclosed within a loop that executes times, using R7 as a counter.

The effect is a 1second delay. First, if the input toggles during the 1 second that the buzzer is sounding, the transition is not detected, since the software is busy in the delay routine. Second, if the input toggles very quickly-in less than a microsecond-the transition may be missed altogether by the JNB and JB instructions.

Problem 5 at the end of this chapter deals with the first situation. The second can only be handled using an interrupt input to "latch" a status flag when a 1-to-0 transition occurs.

This is discussed in Chapter 6. The errors are due to the rounding off, and overhead caused by the time it takes to execute the instructions themselves. What should the reload value of the timer be? Calculate the round-off error if any, and hence determine what crystal frequency would produce no round-off error.

Since the can only handle integer count values, the timer reload value should be counts before overflow, or — Notice that we have rounded off the desired count to an integer value. The round-off error is: Discussion Our previous examples used a crystal frequency of 12 MHz but that causes round-off errors.

Assuming that a count of is used, our goal is to calculate the crystal frequency so that an exact square wave with a frequency of 3 kHz is obtained. The simplest of instructions require one machine cycle while the most complex ones require 4. Therefore, instructions also add to the time delay and if we prefer exact frequencies, we would need to adjust our initial timer counts to compensate for the overhead caused by the execution of these instructions. Example 4.

Only the reload value is different. In this case, a value of was chosen to compensate for the overhead due to instructions. Let's analyze to see why we chose this value. The initial value for P1. Let's assume that P1. The next instruction is JNB which determines the length and duration of the loop, and will be executed repeatedly until the timer 0 overflows. Each execution of JNB requires 2 machine cycles.

When timer 0 overflows, this is the moment in which P1. However, in the above program, P1. This extra delay is the overhead due to instructions. Figure illustrates this in more detail, where the states of P1. Also notice that the actual high- or low-time of the square wave on P1. As shown earlier in Table , five extra special-function registers are added to accommodate Timer 2.

Like Timers 0 and 1, Timer 2 can operate as an interval timer or event counter. The clocking source is provided internally by the on-chip oscillator, or externally by T2, the alternate function of Port 1 bit 0 P1.

Regardless of the clocking source, there are three modes of operation: auto-reload, capture, and baud rate generator. Unlike the reload mode for Timers 0 and 1, Timer 2 is always a full bit timer, even in auto-reload mode. This condition is determined by software or is programmed to generate an interrupt. Either way, TF2 must be cleared by software before it is set again.

EXF2 must be cleared by software. Timer 2 in auto-reload mode is shown in Figure The state of TF2 is tested by software or generates an interrupt. Timer 2 in capture mode is shown in Figure Baud rate generation is discussed in Chapter 5.

The software solutions for the examples presented here feature one common but rather limiting trait. They consume all of the CPU's execution time. The programs execute in wait loops, waiting for a timer overflow. This is fine for learning purposes, but for practical control-oriented applications using microcontrollers, the CPU must perform other duties and respond to external events, such as an operator entering a parameter from a keyboard.

In the chapter on interrupts, we shall demonstrate how to use the timers in an "interrupt-driven" environment. The timer overflow flags are not tested in a software loop but generate an interrupt.

Another program temporarily interrupts the main program while an action is performed that affects the timer interrupt perhaps toggling a port bit. Through interrupts, the illusion of doing several things simultaneously is created. Hint: Don't use the timers. What is the effect of the following instruction? What are the frequency and duty cycle of the waveform created on P1. Rewrite the solution to Example 4. If a 1-to-0 transition occurs while the buzzer is sounding, restart the timing loop to continue the buzz for another second.

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